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? semiconductor components industries, llc, 2008 september, 2008 ? rev. 0 1 publication order number: nlx1g99/d nlx1g99 configurable multifunction gate the nlx1g99 minigate is an advanced high ? speed cmos multifunction gate with a 3 ? state output. with the output enable input (oe ) at high, the output is disabled and is kept at high impedance. with the output enable input (oe ) at low, the device can be configured for logic functions such as mux, and, or, nand, nor, xor, xnor, invert and buffer, depending on the combination of the 4 ? bit input. the device has schmitt ? trigger inputs, thereby enhancing noise immunity. the nlx1g99 input and output structures provide protection when voltages up to 7.0 v are applied, regardless of the supply voltage. features ? high speed: t pd = 6.7 ns (max) @ v cc = 3.3 v ? low power dissipation:i cc = 1 a (max) at t a = 25 c ? power down protection provided on inputs ? balanced propagation delays ? overvoltage tolerant (ovt) input and output pins ? ultra ? small packages ? these are pb ? free devices pin assignment 1 oe 2 a 3 b 4 gnd 5 c 6 d 7 y 8 v cc http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ordering information (top view) oe a b v cc y d pin assignments marking diagrams aa or e = specific device code m = date code = pb ? free package 1 2 3 8 7 6 gnd c 4 5 1 ullga8 1.45 x 1.0 case 613aa 1 ullga8 1.6 x 1.0 case 613ab 1 ullga8 1.95 x 1.0 case 613ac em aam aam
nlx1g99 http://onsemi.com 2 function diagram figure 1. function diagram y a b c d oe function table* input output oe d c b a y l l l l l l l l l l h h l l l h l l l l l h h h l l h l l l l l h l h l l l h h l h l l h h h h l h l l l h l h l l h l l h l h l h l h l h h l l h h l l h l h h l h h l h h h l l l h h h h l h h or l h or l h or l h or l z *to select a logic function, please refer to ?logic configurations? section. function selection logic configuration page 3 ? state buffers 3 3 ? state inverters 3 3 ? state muxes 3 3 ? state and / or / nor 4 3 ? state nand / or 5 3 ? state xor/xnor 6
nlx1g99 http://onsemi.com 3 logic configurations 3 ? state buffer functions available figure 2. oe input y function oe a b c d 3 ? state buffer l input h or l l h h h or l l h or l input h l h or l l l l h input input l h h or l l l l h input input input 3 ? state inverter functions available figure 3. oe input y function oe a b c d 3 ? state buffer l input x l h h h or l h h or l input h l h or l h h l h input input l h h or l h h h l input input input 3 ? state mux functions available figure 4. oe input 1 y input 2 a /b oe input 1 y input 2 a /b function oe a b c d 3 ? state 2 ? to ? 1 3 ? state 2 ? to ? 1 3 ? state 2 ? to ? 1, inverted out 3 ? state 2 ? to ? 1, inverted out l input 1 input 2 input 1 input 2 input 2 input 1 input 2 input 1 input 1 or input 2 input 2 or input 1 input 1 or input 2 input 2 or input 1 l l h h
nlx1g99 http://onsemi.com 4 3 ? state and/nor/or function available figure 5. oe input 1 y input 2 oe input 1 y input 2 no. of inputs and/nand function or/nor function oe a b c d 2 2 3 ? state and 3 ? state and 3 ? state nor 3 ? state nor l l l input 1 input 2 input 2 input 1 l l figure 6. oe input 1 y input 2 oe input 1 y input 2 no. of inputs and/nand function or/nor function oe a b c d 2 2 3 ? state and 3 ? state and 3 ? state nor 3 ? state nor l input 2 h l input 1 input 1 input 2 l h figure 7. oe input 1 y input 2 oe input 1 y input 2 no. of inputs and/nand function or/nor function oe a b c d 2 2 3 ? state and 3 ? state and 3 ? state nor 3 ? state nor l input 1 h l input 2 input 2 input 1 l h figure 8. oe input 1 y input 2 oe input 1 y input 2 no. of inputs and/nand function or/nor function oe a b c d 2 2 3 ? state and 3 ? state and 3 ? state or 3 ? state or l input 1 input 2 h h input 2 input 1 l l
nlx1g99 http://onsemi.com 5 3 ? state nand/or function available figure 9. oe input 1 y input 2 oe input 1 y input 2 no. of inputs and/nand function or/nor function oe a b c d 2 2 3 ? state nand 3 ? state nand 3 ? state or 3 ? state or l l l input 1 input 2 input 2 input 1 h h figure 10. oe input 1 y input 2 oe input 1 y input 2 no. of inputs and/nand function or/nor function oe a b c d 2 2 3 ? state nand 3 ? state nand 3 ? state or 3 ? state or l input 2 h l input 1 input 1 input 2 h l figure 11. oe input 1 y input 2 oe input 1 y input 2 no. of inputs and/nand function or/nor function oe a b c d 2 2 3 ? state nand 3 ? state nand 3 ? state or 3 ? state or l input 1 h l input 2 input 2 input 1 h l figure 12. oe input 1 y input 2 oe input 1 y input 2 no. of inputs and/nand function or/nor function oe a b c d 2 2 3 ? state and 3 ? state and 3 ? state or 3 ? state or l input 1 input 2 h h input 2 input 1 l l
nlx1g99 http://onsemi.com 6 3 ? state xor/xnor function available figure 13. oe input 1 y input 2 function oe a b c d 3 ? state xor l input 1 input 2 h or l h or l l l h or l h or l input 1 input 2 h h l l h h input 1 input 2 input 2 input 1 input 2 input 1 input 2 input 1 figure 14. oe input 1 y input 2 function oe a b c d 3 ? state xor l h l input 1 input 2 figure 15. oe input 1 y input 2 function oe a b c d 3 ? state xor l h l input 1 input 2 figure 16. oe input 1 y input 2 function oe a b c d 3 ? state xnor 3 ? state xnor l h h l l input 1 input 2 input 2 input 1
nlx1g99 http://onsemi.com 7 maximum ratings symbol parameter value unit v cc dc supply voltage ? 0.5 to +7.0 v v in dc input voltage ? 0.5 to +7.0 v v out dc output voltage ? 0.5 to +7.0 v i ik dc input diode current v in < gnd ? 50 ma i ok dc output diode current v out < gnd ? 50 ma i o dc output source/sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range ? 65 to +150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c msl moisture sensitivity level 1 f r flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) > 2000 > 200 n/a v i latchup latchup performance above v cc and below gnd at 125 c (note 5) 500 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. measured with minimum pad spacing on an fr4 board, using 10 mm ? by ? 1 inch, 2 ounce copper trace no air flow. 2. tested to eia / jesd22 ? a114 ? a. 3. tested to eia / jesd22 ? a115 ? a. 4. tested to jesd22 ? c101 ? a. 5. tested to eia / jesd78. recommended operating conditions symbol parameter min max unit v cc positive dc supply voltage 1.65 5.5 v v in digital input voltage 0 5.5 v v out output voltage 0 5.5 v t a operating free ? air temperature ? 55 +125 c t / v input transition rise or fall rate v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v 0 0 0 no limit no limit no limit ns/v
nlx1g99 http://onsemi.com 8 dc electrical characteristics symbol parameter conditions v cc (v) t a = 25 c t a +85 c t a = ? 55 c to +125 c unit min max min max min max v t+ positive threshold voltage 1.65 2.3 3.0 4.5 5.5 0.79 1.11 1.5 2.16 2.61 1.16 1.56 1.87 2.74 3.33 1.16 1.56 1.87 2.74 3.33 1.16 1.56 1.87 2.74 3.33 v v t ? negative threshold voltage 1.65 2.3 3.0 4.5 5.5 0.35 0.58 0.84 1.41 1.78 0.62 0.87 1.19 1.9 2.29 0.35 0.58 0.84 1.41 1.78 0.35 0.58 0.84 1.41 1.78 v v h hysteresis voltage 1.65 2.3 3.0 4.5 5.5 0.30 0.40 0.53 0.71 0.8 0.62 0.8 0.87 1.04 1.2 0.30 0.40 0.53 0.71 0.8 0.62 0.8 0.87 1.04 1.2 0.30 0.40 0.53 0.71 0.8 0.62 0.8 0.87 1.04 1.2 v v oh minimum high ? level output voltage v in = v t ? min or v t+max i oh = ? 50 a 1.65 ? 5.5 v cc ? 0.1 v cc ? 0.1 v cc ? 0.1 v v in = v t ? min or v t+max i oh = ? 4 ma i oh = ? 8 ma i oh = ? 16 ma i oh = ? 24 ma i oh = ? 32 ma 1.65 2.3 3.0 3.0 4.5 1.2 1.9 2.4 2.3 3.8 1.2 1.9 2.4 2.3 3.8 1.2 1.9 2.4 2.3 3.8 v v ol maximum low ? level output voltage v in = v t ? min or v t+max i ol = 50 a 1.65 ? 5.5 0.1 0.1 0.1 v v in = v t ? min or v t+max i ol = 4 ma i ol = 8 ma i ol = 16 ma i ol = 24 ma i ol = 32 ma 1.65 2.3 3.0 3.0 4.5 0.45 0.3 0.4 0.55 0.55 0.45 0.3 0.4 0.55 0.55 0.45 0.3 0.4 0.55 0.55 i in input leakage current 0 v in 5.5 v 0 ? 5.5 0.1 1.0 1.0 a i off power off leakage current v in or v o = 5.5 v 0 1.0 10 10 a i oz tri ? state output leakage current v o = v cc or gnd 1.65 ? 5.5 1.0 10 10 a i cc quiescent supply current v in = v cc or gnd, i o = 0 1.65 ? 5.5 1.0 10 10 a i cc increase in i cc per input one input at (v cc ? 0.6) v, other inputs at v cc or gnd 3 ? 5.5 10 100 100 a
nlx1g99 http://onsemi.com 9 ac electrical characteristics (input t r = t f = 3.0 ns) symbol parameter v cc (v) test condition t a = 25 c t a +85 c t a = ? 55 c to +125 c unit min typ max min max min max t plh , t phl propagation delay, any input to output y (see test circuit) 1.65 ? 1.95 2.3 ? 2.7 3.0 ? 3.6 4.5 ? 5.5 refer to switch positions and loading conditions in figure 17 to 21. 4.3 2.4 1.7 1.3 12.8 7.1 5.2 4.0 25.1 10.2 6.7 4.5 4.3 2.4 1.7 1.3 25.1 10.2 6.9 4.9 4.3 2.4 1.7 1.3 25.1 10.2 7.0 5.0 ns t en output enable time, oe to y 1.65 ? 1.95 2.3 ? 2.7 3.0 ? 3.6 4.5 ? 5.5 refer to switch positions and loading conditions in figure 17 to 21. 3.4 2.1 1.3 1.0 24.7 11 7.5 5.7 3.4 2.1 1.3 1.0 24.7 12 8.0 6.2 3.4 2.1 1.3 1.0 24.7 12.2 8.3 6.5 ns t dis output disable time, oe to y 1.65 ? 1.95 2.3 ? 2.7 3.0 ? 3.6 4.5 ? 5.5 refer to switch positions and loading conditions in figure 17 to 21. 4.0 2.7 3.5 2.0 15.5 7.5 7.0 5.5 4.0 2.7 3.5 2.0 15.5 7.5 7.0 5.5 4.0 2.7 3.5 2.0 15.5 7.5 7.0 5.5 ns t plh , t phl propagation delay, any input to output y (see test circuit) 1.65 ? 1.95 2.3 ? 2.7 3.0 ? 3.6 4.5 ? 5.5 refer to switch positions and loading conditions in figure 22 to 26. 4.3 2.5 2.3 1.6 13.6 7.8 5.6 4.4 25.7 10.7 7.6 5.2 4.3 2.5 2.3 1.6 25.7 10.7 7.6 5.2 4.3 2.5 2.3 1.6 25.7 10.7 7.6 5.2 ns t en output enable time, oe to y 1.65 ? 1.95 2.3 ? 2.7 3.0 ? 3.6 4.5 ? 5.5 refer to switch positions and loading conditions in figure 22 to 26. 4.2 2.4 2.0 1.7 25.2 11.3 8.0 6.0 4.2 2.4 2.0 1.7 25.2 12.2 8.5 6.5 4.2 2.4 2.0 1.7 25.2 13 8.7 6.7 ns t dis output disable time, oe to y 1.65 ? 1.95 2.3 ? 2.7 3.0 ? 3.6 4.5 ? 5.5 refer to switch positions and loading conditions in figure 22 to 26. 3.7 2.0 2.1 1.0 15 6.5 5.6 4.5 3.7 2.0 2.1 1.0 15 6.7 5.8 4.7 3.7 2.0 2.1 1.0 15 6.9 5.9 4.9 ns c in input capacitance 3.3 3.5 pf c o output capacitance 3.3 6.0 pf c pd power dissipation capacitance (note 6) 3.3 f = 10 mhz 22 pf 6. c pd is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without load. average operating current can be obtained by the equation i cc(opr) = c pd ? v cc ? f in + i cc . c pd is used to determine the no ? load dynamic power consumption: p d = c pd ? v cc 2 ? f in + i cc ? v cc.
nlx1g99 http://onsemi.com 10 test circuit and voltage waveforms figure 17. load circuit r l c l * from output under test gnd open v load r l s1 *c l includes probes and jig capacitance. test s1 t plh /t phl open t plz /t pzl v load t phz /t pzh gnd v cc inputs v m v load c l r l v v i t r /t f 1.8 v 0.15 v v cc 2 ns v cc /2 2 x v cc 15 pf 1 m 0.15 v 2.5 v 0.2 v v cc 2 ns v cc /2 2 x v cc 15 pf 1 m 0.15 v 3.3 v 0.3 v 3 v 2.5 ns 1.5 v 6 v 15 pf 1 m 0.3 v 5.5 v 0.5 v v cc 2.5 ns v cc /2 2 x v cc 15 pf 1 m 0.3 v figure 18. voltage waveforms pulse duration figure 19. voltage waveforms setup and hold times figure 20. voltage waveforms propagation delay times inverting and noninverting outputs figure 21. voltage waveforms enable and disable times low ? and high ? level enabling input input output output v m v load /2 v m t w v i 0 v v m v m v m v m v m v m v i 0 v t plh t phl t phl t plh v oh v ol v oh v ol output control v i 0 v v m v m v m v m t pzh t phz v ol v oh 0 v output output waveform 1 s1 at v load (note 7) waveform 2 s1 at gnd (note 7) v i 0 v timing input data input v i 0 v v m v m v m t su t h v ol + v v oh ? v 7. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control 8. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 . 9. the outputs are measured one at a time, with one transition per measurement. 10. all parameters are waveforms are not applicable to all devices.
nlx1g99 http://onsemi.com 11 figure 22. load circuit r l c l * from output under test gnd open v load r l *c l includes probes and jig capacitance. s1 test s1 t plh /t phl open t plz /t pzl v load t phz /t pzh gnd v cc inputs v m v load c l r l v v i t r /t f 1.8 v 0.15 v v cc 2 ns v cc /2 2 x v cc 30 pf 1 k 0.15 v 2.5 v 0.2 v v cc 2 ns v cc /2 2 x v cc 30 pf 500 0.15 v 3.3 v 0.3 v 3 v 2.5 ns 1.5 v 6 v 50 pf 500 0.3 v 5.5 v 0.5 v v cc 2.5 ns v cc /2 2 x v cc 50 pf 500 0.3 v figure 23. voltage waveforms pulse duration figure 24. voltage waveforms setup and hold times figure 25. voltage waveforms propagation delay times inverting and noninverting outputs figure 26. voltage waveforms enable and disable times low ? and high ? level enabling input input output output v m v load /2 v m t w v i 0 v v m v m v m v m v m v m v i 0 v t plh t phl t phl t plh v oh v ol v oh v ol output control v i 0 v v m v m v m v m t pzh t phz v ol v oh 0 v output output waveform 1 s1 at v load (note 11) waveform 2 s1 at gnd (note 11) v i 0 v timing input data input v i 0 v v m v m v m t su t h v ol + v v oh ? v 11. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control . waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control 12. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 . 13. the outputs are measured one at a time, with one transition per measurement. 14. all parameters are waveforms are not applicable to all devices.
nlx1g99 http://onsemi.com 12 ordering information device package shipping ? NLX1G99AMX1TCG ullga8 ? 0.5p (pb ? free) 3000 / tape & reel nlx1g99bmx1tcg ullga8 ? 0.4p (pb ? free) 3000 / tape & reel nlx1g99cmx1tcg ullga8 ? 0.35p (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nlx1g99 http://onsemi.com 13 package dimensions ullga8 1.45x1.0, 0.35p case 613aa ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. a maximum of 0.05 pull back of the plated terminal from the edge of the package is allowed. a b e d bottom view b e 8x 0.10 b 0.05 a c c l 7x note 3 0.10 c pin one reference top view 0.10 c 8x a a1 0.05 c 0.05 c c seating plane side view l1 1 4 5 8 dim min max millimeters a ??? 0.40 a1 0.00 0.05 b 0.15 0.25 d 1.45 bsc e 1.00 bsc e 0.35 bsc l 0.25 0.35 l1 0.30 0.40 e/2 note 4 soldermask defined* dimensions: millimeters 0.22 7x 0.48 8x 1.18 0.53 pitch *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 0.35 1 mounting footprint pkg outline
nlx1g99 http://onsemi.com 14 package dimensions ullga8 1.6x1.0, 0.4p case 613ab ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. a maximum of 0.05 pull back of the plated terminal from the edge of the package is allowed. a b e d bottom view b e 8x 0.10 b 0.05 a c c l 7x note 3 0.10 c pin one reference top view 0.10 c 8x a a1 0.05 c 0.05 c c seating plane side view l1 1 4 5 8 dim min max millimeters a ??? 0.40 a1 0.00 0.05 b 0.15 0.25 d 1.60 bsc e 1.00 bsc e 0.40 bsc l 0.25 0.35 l1 0.30 0.40 e/2 note 4 soldermask defined* dimensions: millimeters 0.26 7x 0.49 8x 1.24 0.53 pitch *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 0.40 1 mounting footprint pkg outline
nlx1g99 http://onsemi.com 15 package dimensions ullga8 1.95x1.0, 0.5p case 613ac ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. a maximum of 0.05 pull back of the plated terminal from the edge of the package is allowed. a b e d bottom view b e 8x 0.10 b 0.05 a c c l 7x note 3 0.10 c pin one reference top view 0.10 c 8x a a1 0.05 c 0.05 c c seating plane side view l1 1 4 5 8 dim min max millimeters a ??? 0.40 a1 0.00 0.05 b 0.15 0.25 d 1.95 bsc e 1.00 bsc e 0.50 bsc l 0.25 0.35 l1 0.30 0.40 e/2 note 4 soldermask defined* dimensions: millimeters 0.30 7x 0.49 8x 1.24 0.53 pitch *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 0.50 1 mounting footprint pkg outline on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nlx1g99/d minigate is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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